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Keep-H's Hardware Design Study Notes
5 본문
I. Introduction
A. Background and Motivation
B. Related Work and Limitations
C. Contributions
II. Background
A. Battery SOC Estimation
B. Temporal Convolutional Network
C. Low-Bit/Ternary Quantization
III. Proposed 1.58-bit Ternary TCN for SOC Estimation
A. Overall Framework
B. Multi-Scale TCN Architecture
C. 1.58-bit Ternary Quantization
D. Hardware-Aware Fixed-Point Inference
E. Temperature-Robust Training Strategy
IV. Dataset and Experimental Setup
A. Battery Dataset and Driving Profiles
B. Preprocessing and Window Generation
C. Baseline Models
D. Evaluation Metrics
E. Hardware Evaluation Setup
V. Results and Discussion
A. Overall SOC Estimation Accuracy
B. Temperature-wise Evaluation
C. Driving Profile-wise Evaluation
D. Comparison With LSTM, 1D CNN, and TCN Baselines
E. Accuracy–Memory Trade-off
F. Ablation Study
G. Hardware Implementation Results
VI. Conclusion